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ISL59885
Data Sheet September 8, 2005 FN7442.3
Auto-Adjusting Sync Separator for HD and SD Video
The ISL59885 video sync separator is manufactured using high performance analog CMOS process. This device extracts ISL59885 sync timing information from both standard and non-standard video input in the presence of Macrovision pulses. It provides composite sync, vertical sync, SD and HDTV detection, and horizontal sync outputs. Fixed 70mV sync tip slicing provides sync edge detection when the video input level is between 0.5VP-P and 2VP-P. Timing is adjusted automatically for various video standards. The composite sync output follows sync pulses and a vertical sync pulse is output on the rising edge of the first vertical serration following the vertical pre-equalizing string. For non-standard vertical inputs, a default vertical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. The horizontal output gives horizontal timing with pre/post equalizing pulses. ISL59885 has an auto input frequency detect feature that sets the right timing for any input format. The ISL59885 is available in an 8 Ld SO package and is specified for operation over the full -40C to +85C temperature range.
Features
* NTSC, PAL, SECAM, HDTV, non-standard video sync separation * Fixed 70mV slicing of video input levels from 0.5VP-P to 2VP-P * Single 3V to 5V supply * Composite sync output * Vertical output * Horizontal output * HDTV detection * 81% to 90% Hsync blanking window (R5218) * Macrovision compatible * Available in 8 Ld SO package * Pb-Free plus anneal available (RoHS compliant)
Applications
* High definition video equipment
Demo Board
* A dedicated demo board is available
Ordering Information
PART NUMBER ISL59885IS ISL59885IS-T7 ISL59885IS-T13 ISL59885ISZ (See Note) ISL59885ISZ-T7 (See Note) ISL59885ISZ-T13 (See Note) ISL59885ISR5218 ISL59885ISZR5218 ISL59885IS-T7R5218 ISL59885ISZ-T7R5218 ISL59885IS-T13R5218 ISL59885ISZ-T13R5218 PACKAGE 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO (Pb-Free) 8 Ld SO (Pb-Free) 8 Ld SO (Pb-Free) 8 Ld SO 8 Ld SO (Pb-Free) 8 Ld SO 8 Ld SO (Pb-Free) 8 Ld SO 8 Ld SO (Pb-Free) TAPE & REEL 7" 13" 7" 13" 7" 7" 13" 13" PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
Pinout
ISL59885 (8 LD SO) TOP VIEW
COMPOSITE SYNC OUT 1 COMPOSITE VIDEO IN 2 VERTICAL SYNC OUT 3 GND 4 8 VDD 7 HORIZONTAL OUTPUT 6 CSET 5 HD
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59885
Absolute Maximum Ratings (TA = 25C)
VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER IDD, Quiescent Clamp Voltage Clamp Discharge Current Clamp Charge Current VOL Output Low Voltage VOH Output High Voltage
VDD = 3.3V, TA = 25C, CSET = 56nF, unless otherwise specified. DESCRIPTION VDD = 3.3V Pin 2, ILOAD = -100A Pin 2 = 2V Pin 2 = 1V IOL = 1.6mA IOH = -40A IOH = -1.6mA 3 2.5 MIN 1.5 1.35 6 -9 TYP 2.2 1.5 15 -7.2 0.24 3.2 3.0 MAX 4 1.65 30 -5.2 0.5 UNIT mA V A mA V V V
Dynamic Characteristics
PARAMETER Comp Sync Prop Delay, tCS Horizontal Sync Delay, tHS Horizontal Sync Width, tHS-PW Vertical Sync Width, tVS Vertical Sync Default Delay, tVSD Hsync Blanking Window Input Dynamic Range Slice Level HD Pin Level See Figure 9 See Figure 9 See Figure 9 Normal or default trigger, 50% - 50%, see Figure 7 See Figure 10 ISL59885IS-R5218 only Video input amplitude to maintain slice level spec, VDD = 3.3V VSLICE above VCLAMP 720p, 1080i, 1080p 3.8 230 28 81 0.5 50 70 0 DESCRIPTION MIN TYP 35 40 5.2 280 50 85 MAX 75 80 6.2 350 68 90 2 90 UNIT ns ns s s s % VP-P mV V
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME COMPOSITE SYNC OUT COMPOSITE VIDEO IN VERTICAL SYNC OUT GND HD CSET HORIZONTAL OUTPUT VDD PIN FUNCTION Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase) Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period Supply ground Low when input horizontal frequency is greater than 20kHz (An external capacitor to ground); bypass pin for internal bias generator. Horizontal output; falling edge active Positive supply
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FN7442.3 September 8, 2005
ISL59885 Typical Performance Curves
VS=3.3V & 5.0V HSYNC PULSEWIDTH (ns)
VS=3.3V & 5.0V
VCSET (V)
HSYNC (kHz)
HSYNC FREQUENCY (kHZ)
FIGURE 1. HSYNC vs VCSET (RSET = OPEN)
FIGURE 2. HSYNC PULSEWIDTH vs HSYNC FREQUENCY (RSET = OPEN)
HSYNC BLANKING TIME (s)
VS=3.3V & 5.0V 0.5V/DIV 5V/DIV 5V/DIV VIN HSYNC VSYNC
5V/DIV
CSYNC
100s/DIV VCSET (V)
FIGURE 3. HSYNC vs VCSET (RSET = OPEN)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
FIGURE 4. MACROVISION COMPATIBILITY (NTSC)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.8 1.6 POWER DISSIPATION (W) 1.4
1.2 POWER DISSIPATION (W) 1 0.8 0.6 0.4 0.2 0
1.2 1.136W 1 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150
J
A =1
781mW
J SO 8 60 C /W
SO 8 10 C /W
A =1
0
25
50
75 85 100
125
150
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7442.3 September 8, 2005
ISL59885
SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE 1.5s 0.1s TIME 3H 1 2 3 4 VERTICAL BLANKING INTERVAL = 20H 3H 5 6 7 3H 8 9 10 19 20 21 +63.5s +H 1271s -0s -H
H SYNC INTERVAL H
START OF FIELD ONE
H
H VERTICAL SYNC PULSE INTERVAL 9 LINE VERTICAL INTERVAL
0.5H POST-EQUALIZING PULSE INTERVAL
H
PRE-EQUALIZING PULSE INTERVAL
REF SUBCARRIER PHASE, COLOR FIELD ONE
SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1
SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3
tVS SIGNAL 1d. HORIZONTAL SYNC OUTPUT, PIN 7
NOTES: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. Horizontal sync output produces the true "H" pulses of nominal width of 5s. It has the same delay as the composite sync. FIGURE 7. TIMING DIAGRAM
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FN7442.3 September 8, 2005
ISL59885
CONDITIONS: VCCA1 = VCCA2 = VCCD = +5V, TA = 25C, NO FILTER (REGISTER 2 BIT 4=0)
INPUT DYNAMIC SYNC LEVEL RANGE 0.5V-2V (@VCCA1=5V) SYNC IN 0.5V-1V (@VCCA1=3.3V) 50%
COLOR BURST
WHITE LEVEL VIDEO
VSLICE VSYNC (SYNC TIP VOLTAGE)
VBLANK (BLANKING LEVEL VOLTAGE)
SYNC
SYNC TIP tdSYNCOUT SYNC OUT
DEPENDS ON WIDTH OF INPUT SYNC AT 50% LEVEL
HOUT
tdHOUT
THOUT
FIGURE 8. HORIZONTAL INTERVAL 525/625 LINE COMPOSITE TYP (Note 1) 65 470 5.2
PARAMETER tdSYNCOUT tdHOUT THOUT NOTE:
DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input Horizontal Output Width See Figure 8 See Figure 8 See Figure 8
CONDITIONS
UNIT ns ns us
1. Delay variation is less than 2.5ns over temperature range.
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ISL59885
SIGNAL 2a. COMPOSITE VIDEO INPUT 70mV tCS COMP SYNC PROP DELAY SIGNAL 2b. COMPOSITE SYNC OUTPUT
SLICE LEVEL
SIGNAL 2c. VERTICAL SYNC OUTPUT
tCS-VS COMP SYNC VERT SYNC DELAY
SIGNAL 2d. HORIZONTAL SYNC OUTPUT
tHS tHS-PW
FIGURE 9. STANDARD VERTICAL TIMING
LINES SIGNAL 3a. COMPOSITE VIDEO INPUT 2 3 4 5 (NO VERTICAL SYNC PULSES) VERT SYNC DEFAULT DELAY
tVSD SIGNAL 3b. VERTICAL SYNC OUTPUT
FIGURE 10. NON-STANDARD VERTICAL TIMING
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FN7442.3 September 8, 2005
ISL59885
COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE START OF FIELD ONE 622 623 624 625 1 2 3 4 5 6 7 23 24
SYNCOUT OUTPUT
VOUT OUTPUT
TVS
HOUT OUTPUT
NOTES: b. The composite sync output reproduces all the video input sync pulses, with a propagation delay. c. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay.
FIGURE 11. EXAMPLE OF VERTICAL INTERVAL (625)
SYNCIN 1123 SYNCOUT 1124 1125 1 2 3 4 5 6 7 8 ... 21
HOUT
VOUT
SYNCIN 560 SYNCOUT 561 562 563 564 565 566 567 568 569 570 ... 583
HOUT
VOUT
FIGURE 12. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED
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FN7442.3 September 8, 2005
ISL59885
SYNCIN 1245 SYNCOUT 1246 1247 1248 1249 1250 1 2 3 4 5 ... 48
HOUT
VOUT
SYNCIN 620 SYNCOUT 621 622 623 624 625 626 627 628 629 630 ... 673
HOUT VOUT
FIGURE 13. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED (1250 LINES)
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FN7442.3 September 8, 2005
ISL59885
CONDITIONS: VCCA1 = VCCA2 = VCCD = +3.3V/+5V, TA = 25C, NO FILTER (REGISTER 2 BIT 4=0)
SYNCIN
SYNC OUT
tdSYNCOUT
HOUT
tdHOUT
THOUT
FIGURE 14. HORIZONTAL INTERVAL (HDTV) (720p)
H Timing for HDTV, No Filter (using 720p input signal)
PARAMETER tdSYNCOUT tdHOUT THOUT NOTE: 1. Delay variation is less than 2.5ns over temperature range. DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input Horizontal Output Width See Figure 14 See Figure 14 See Figure 14 CONDITIONS TYP TYP @ 5V @ 3.3V (Note 1) (Note 1) 56 48 1.90 50 36 1.90 UNIT ns ns us
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FN7442.3 September 8, 2005
ISL59885
CONDITIONS: VCCA1 = VCCA2 = VCCD = +3.3V/+5V, TA = 25C, FILTER (REGISTER 2 BIT 4=1)
SYNCIN
SYNC OUT
tdSYNCOUT
HOUT
tdHOUT
THOUT
FIGURE 15. HORIZONTAL INTERVAL (HDTV) (720p)
H Timing for HDTV, With Filter (using 720p input)
PARAMETER tdSYNCOUT tdHOUT THOUT NOTE: 1. Delay variation is less than 2.5ns over temperature range. DESCRIPTION SYNCOUT Timing Relative to Input HOUT Timing Relative to Input Horizontal Output Width See Figure 15 See Figure 15 See Figure 15 CONDITIONS TYP TYP @ 5V @ 3.3V (Note 1) (Note 1) 120 112 200 110 100 200 UNIT ns ns ns
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FN7442.3 September 8, 2005
ISL59885 Applications Information
Video In
A simplified block diagram is shown following page. An AC coupled video signal is input to Video In pin 2 via C1, nominally 0.1F. Clamp charge current will prevent the signal on pin 2 from going any more negative than Sync Tip Ref, about 1.5V. This charge current is nominally about 1mA. A clamp discharge current of about 10A is always attempting to discharge C1 to Sync Tip Ref, thus charge is lost between sync pulses that must be replaced during sync pulses. The droop voltage that will occur can be calculated from IT = CV, where V is the droop voltage, I is the discharge current, T is the time between sync pulses (sync period sync tip width), and C is C1. An NTSC video signal has a horizontal frequency of 15.73kHz, and a sync tip width of 4.7s. This gives a period of 63.6s and a time T = 58.9s. The droop voltage will then be V = 5.9mV. This is less than 2% of a nominal sync tip amplitude of 286mV. The charge represented by this droop is replaced in a time given by T = CV/I, where I = clamp charge current = 5.3mA. Here T = 590ns, about 12% of the sync pulse width of 4.7s. It is important to choose C1 large enough so that the droop voltage does not approach the switching threshold of the internal comparator. present on the I/P signal after the true H sync will be ignored, thus the horizontal output will not be affected by MacroVision copy protection. When loss of sync, the Horizontal Sync output is held high.
CSET
An external CSET capacitor connected from CSET pin 6 to ground. CSET capacitor should be a X7R grade or better as the Y5U general use capacitors may be too leaky and cause faulty operation. The CSET capacitor should be very close to the CSET pin to reduce possible board leakage. 56nF is recommended. CSET simplified block diagram is shown in diagram 5. The CSET capacitor rectifies 5us pulse current and creates a voltage on CSET. The CSET voltage is converted to bias current for HSYNC and VSYNC timing.
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the incoming video signal. Use of the optional chroma filter is shown in the figure below. It can be implemented very simply and inexpensively with a series resistor of 100 and a capacitor of 570pF, which gives a single pole roll-off frequency of about 2.79MHz during NTSC or PAL. This sufficiently attenuates the 3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet passes the approximately 15kHz sync signals without appreciable attenuation. During HDTV, the transistor turns off and a 100pF capacitor is left to filter any noise present at the input. A chroma filter will increase the propagation delay from the composite input to the outputs.
CHROMA FILTER VIDEO IN RF 100 CF 100pF 0.1F ISL59885 1 CSYNC VDD 2 CVIN HOUT 8 7 6 5
Composite Sync
The Composite Sync output is simply a reproduction of the input signal with the active video removed. The sync tip of the Composite video signal is clamped to 1.5V at pin 2 and then slices at 70mV above the sync tip reference. The output signal is buffered out to pin 1. When loss of sync, the Composite Sync output is held low.
Vertical Sync
A low-going Vertical Sync pulse is output during the start of the vertical cycle of the incoming video signal. The vertical cycle starts with a pre-equalizing phase of pulses with a duty cycle of about 93%, followed by a vertical serration phase that has a duty cycle of about 15%. Vertical Sync is clocked out of the ISL59885 on the first rising edge during the vertical serration phase. In the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 60s after the last falling edge of the vertical equalizing phase.
3 VSYNC CSET CF2 470pF 4 GND HD
10k MMBT3904
HD-Detect
High definition video is flagged by HD going low when the input horizontal frequency is greater than 20kHz.
Horizontal Sync
The horizontal circuit senses the composite sync edges and produces the true horizontal pulses of nominal width 5.2s. The leading edge is triggered from the leading edge of the input H sync, with the same propagation delay as composite sync. The half line pulses present in the input signal during vertical blanking are removed with an internal 2H line eliminator circuit. This is a circuit that inhibits horizontal output pulses until 75% of the line time is reached, then the horizontal output operation is enabled again. Any signals 11
FN7442.3 September 8, 2005
ISL59885 Simplified Block Diagram
CLAMP SYNC TIP REF 1.5V COMPOSITE VIDEO IN 2 SLICE 1.57V GND 4 CSET C3 56nF SYNC TIP 70mV SLICE HD DETECTOR 5 HD VDD 8 VDD 5V C2 0.1F COMP. + 1 COMPOSITE SYNC
RF 620 CF 510pF
C1 0.1F
6
REF GEN
V SYNC
3 VERTICAL SYNC OUT
H SYNC
7 HORIZONTAL SYNC OUT
2H ELIMINATOR
CSET Bias Circuit
VDD VDD
CSYNC
PULSE 5s
CSET 56nF
+ IBIAS - TIMING
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FN7442.3 September 8, 2005
ISL59885 Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7442.3 September 8, 2005

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